1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device and the semiconductor integrated circuit device, and more particularly to a method of carrying out adjustment to adapt the clock delay values of a clock input terminal and a clock input circuit to be operated in response to a clock signal such as a flip-flop circuit in each hierarchical block.
2. Description of the Related Art
In a method of synchronously adjusting a clock delay among hierarchical blocks 902, 903, 904 and 905 in the layout design of a semiconductor integrated circuit device, conventionally, a clock input terminal 907 is formed on the outer periphery of each of the hierarchical blocks 902 to 905 as shown in FIG. 10. There is employed a method of clock-distributing and connecting the wiring of a clock line by a so-called equal-length wiring for wiring on a hierarchical top in such a manner that the length of a wiring 901 (a wiring length) is equal in order to synchronize the arrival time of a clock signal between the clock input terminal 907 and a clock input terminal 900 of a semiconductor chip to be the supply source of a clock signal. Thus, a clock delay to each hierarchical block is adjusted to be synchronized (for example, see JP-A-5-198674 gazette (Pages 1 to 4, FIG. 1)). 906 denotes the boundary of a semiconductor chip.
Moreover, there has been a technique for wiring and connecting a mutual signal between hierarchical blocks in which a signal terminal is formed on the hierarchical block and mutual signals between the blocks are wired and connected (for example, see JP-A-5-243380 gazette (Paragraph 1, FIG. 2)).
However, a clock delay adjusting method of synchronously adjusting a clock delay between hierarchical blocks in the layout design of the conventional semiconductor integrated circuit device synchronizes a clock delay up to the clock terminal of a clock input circuit which is a circuit to be operated synchronously with the clocks of all flip-flops in the hierarchical block on and after one point of the clock input terminal formed on the outer periphery of the hierarchical block, and furthermore, is executed on the condition that a clock delay for each hierarchical block is synchronized.
In the case in which a hierarchical block having a large circuit scale and a large block size is provided on a semiconductor chip, however, there are a large number of arrangement conditions that the position of arrangement of the clock input circuit in the hierarchical block is gathered closely or distributed depending on the circuit conditions of the hierarchical block. Therefore, it is hard to synchronize the clock delay only on and after one point of the clock input terminal formed on the outer periphery of the hierarchical block. In the actual development of the semiconductor integrated circuit device, furthermore, such a case is really caused very often. Similarly, it is very hard to synchronize the clock delay of each hierarchical block.
In the conventional method, therefore, there has been a problem in that the clock delay of a semiconductor integrated circuit device cannot be adjusted to be synchronized because of the presence of a block having a clock delay in a hierarchical block which is not synchronized even if the clock input terminal of each hierarchical block and the clock input terminal of a semiconductor chip are clock distributed by an equal-length wiring over a hierarchical top to execute the wiring connection of a clock line to synchronize the arrival time of a clock signal.